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Gate static pin_memory on the host-RAM budget (fixes #13730)
On AMD/ROCm a clean launch stalls at "Requested to load LTXAV" while system RAM fills and spills to swap, even though VRAM sits at ~65%. It is host-side pinned-memory exhaustion, not VRAM pressure. partially_load() pins every offloaded weight via the static path pin_memory, which ignores ensure_pin_registerable()'s result and unconditionally cudaHostRegisters up to MAX_PINNED_MEMORY (0.90*RAM on Linux). Those pins are only reclaimable from is_dynamic() models by free_registrations, and dynamic VRAM is off by default on AMD, so they are never reclaimable. Page-locked RAM is not swappable, so the loader exhausts RAM and thrashes. The dynamic-VRAM pin path (comfy/pinned_memory.py) already guards this with ensure_pin_budget/ensure_pin_registerable; only the static path was missing it. Gate pin_memory the same way and skip pinning when the budget cannot be met (the weight stays in pageable RAM, still correct, just not page-locked). Behavior is unchanged when RAM is ample and under --high-ram.
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@ -1534,7 +1534,14 @@ def pin_memory(tensor):
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size = tensor.nbytes
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comfy.memory_management.extra_ram_release(comfy.memory_management.RAM_CACHE_HEADROOM)
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ensure_pin_registerable(size)
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# Respect the host-RAM budget like the dynamic-VRAM pin path (comfy/pinned_memory.py)
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# already does. Without this gate the static load path keeps cudaHostRegister-ing
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# offloaded weights toward MAX_PINNED_MEMORY (90% of RAM on Linux) regardless of how
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# little RAM is actually free, so unswappable pages fill RAM+swap and large model
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# loads stall (issue #13730). When the budget cannot be met, skip pinning and leave
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# the weight in pageable RAM (still correct, just not pinned).
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if not ensure_pin_budget(size) or not ensure_pin_registerable(size):
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return False
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ptr = tensor.data_ptr()
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if ptr == 0:
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